Semiconductor memory began in the 1960s with bipolar memory, which used bipolar transistors. Although it was faster, it could not compete with the lower price of magnetic core memory. [10] MOS RAM Yao Z, Dong Z, Zheng Z, Gholami A, Yu J, Tan E, Wang L, Huang Q, Wang Y, Mahoney MW, Keutzer K. HAWQV3: Dyadic Neural Network Quantization. arXiv preprint arXiv:2011.10680. 2020 Nov 20. Coudrain P, Charbonnier J, Garnier A, et al. Active interposer technology for chiplet-based advanced 3D system architectures. In: Proceedings of 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, 2019. 569–578 a b c "Electronic Design". Electronic Design. Hayden Publishing Company. 41 (15–21). 1993. The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems. Direct RDRAM" (PDF). Rambus. 12 March 1998. Archived (PDF) from the original on 2019-06-21 . Retrieved 21 June 2019.

The new architectures the CRISP collaborators are developing integrate processing and memory into a single unit. By tightly coupling the processing into the data storage, the processing rate can be dramatically increased. History These IBM tabulating machines from the mid-1930s used mechanical counters to store information. 1- megabit (Mbit) chip, one of the last models developed by VEB Carl Zeiss Jena in 1989 Effective mitigations would require accelerated pathways to understanding the virus’ methods of transmission and mutation. Large numbers of biological samples from humans infected by the virus were being collected from wastewater on the UC San Diego campus, and these could be used to sequence the virus to get at this information. K4W1G1646G-BC08 Datasheet" (PDF). Samsung Electronics. November 2010. Archived (PDF) from the original on 2022-01-24 . Retrieved 10 July 2019.In today's technology, random-access memory takes the form of integrated circuit (IC) chips with MOS (metal–oxide–semiconductor) memory cells. RAM is normally associated with volatile types of memory where stored information is lost if power is removed. The two main types of volatile random-access semiconductor memory are static random-access memory (SRAM) and dynamic random-access memory (DRAM).

Williams, F. C.; Kilburn, T. (Sep 1948), "Electronic Digital Computers", Nature, 162 (4117): 487, Bibcode: 1948Natur.162..487W, doi: 10.1038/162487a0, S2CID 4110351. Reprinted in The Origins of Digital Computers. MOS memory, based on MOS transistors, was developed in the late 1960s, and was the basis for all early commercial semiconductor memory. The first commercial DRAM IC chip, the 1K Intel 1103, was introduced in October 1970. Shahidi, Ghavam G.; Davari, Bijan; Dennard, Robert H.; Anderson, C. A.; Chappell, B. A.; etal. (December 1994). "A room temperature 0.1 μm CMOS on SOI". IEEE Transactions on Electron Devices. 41 (12): 2405–2412. Bibcode: 1994ITED...41.2405S. doi: 10.1109/16.337456. S2CID 108832941. a b c d e "Late 1960s: Beginnings of MOS memory" (PDF). Semiconductor History Museum of Japan. 2019-01-23 . Retrieved 27 June 2019.

Iandola FN, Shaw AE, Krishna R, Keutzer KW. SqueezeBERT: What can computer vision teach NLP about efficient neural networks?. arXiv preprint arXiv:2006.11316. 2020 Jun 19.

In the other stories, too, Doerr moves with grace between the larger rhythms of the natural world and the closed worlds of individual consciousness. In "Procreate, Generate", a couple struggle to conceive as the seasons turn; the wryly conversational, heartbreaking "The River Nemunas" sees an American teenage orphan start a new life in Lithuania; in "Village 123", a Chinese seed keeper anticipates the submersion of her village as part of a new dam project. This last story falls victim to the normally fastidious Doerr's weakness for overexplicitness: memory, we are told sternly and repeatedly, is a seed – "it is a village slated to be inundated". Since 2006, " solid-state drives" (based on flash memory) with capacities exceeding 256 gigabytes and speeds far exceeding traditional disks have become available. This development has started to blur the definition between traditional random-access memory and "disks", dramatically reducing the difference in speed. Havemann, Robert H.; Eklund, R. E.; Tran, Hiep V.; Haken, R. A.; Scott, D. B.; Fung, P. K.; Ham, T. E.; Favreau, D. P.; Virkus, R. L. (December 1987). "An 0.8 μm 256K BiCMOS SRAM technology". 1987 International Electron Devices Meeting. pp.841–843. doi: 10.1109/IEDM.1987.191564. S2CID 40375699. a b c "Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option". Samsung Electronics. Samsung. 10 February 1999 . Retrieved 23 June 2019. Fine CMOS techniques create 1M VSRAM". Japanese Technical Abstracts. University Microfilms. 2 (3–4): 161. 1987.

AI加速器的设计

Synchronous dynamic random-access memory (SDRAM) later debuted with the Samsung KM48SL2000 chip in 1992. The Cutting Edge of IC Technology: The First 294,912-Bit (288K) Dynamic RAM". National Museum of American History. Smithsonian Institution . Retrieved 20 June 2019. Boroumand A, Zheng H, Mutlu O, et al. CoNDA: efficient cache coherence support for near-data accelerators. In: Proceedings of ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA), Phoenix, 2019. 629–642 Toshiba's new 32 Mb Pseudo-SRAM is no fake". The Engineer. 24 June 2001. Archived from the original on 29 June 2019 . Retrieved 29 June 2019.

IBM Archives -- FAQ's for Products and Services". ibm.com. Archived from the original on 2012-10-23. Part of this section is transcluded from Synchronous dynamic random-access memory. ( edit| history) Synchronous dynamic random-access memory (SDRAM) AI 模型的训练时，这些设计上的趋势已经显得捉襟见肘，特别是对于 NLP 和 推荐系统相关的模型：有通信带宽瓶颈。事实上，芯片内部、芯片间还有 AI 硬件之间的通信，都已成为不少 AI 应用的瓶颈。特别是最近大火的 Transformer 类模型，模型大小平均每两年翻240倍（如图表2所示）。类似的，大规模的推荐系统模型，模型大小已经达到了 O(10) TB 的级别了。与之相比，AI 硬件上的内存大小仅仅是以每两年翻2倍的速率在增长。 NLP 中的 SOTA Transformer 类模型的算力需求，以每两年750倍的速率增长，模型参数数量则以每两年240倍的速率增长。相比之下，硬件算力峰值的增长速率为每两年3.1倍。DRAM 还有硬件互连带宽增长速率则都为每两年1.4倍，已经逐渐被需求甩在身后。深入思考这些数字，过去20年内硬件算力峰值增长了90000倍，但是DRAM/硬件互连带宽只增长了30倍。在这个趋势下，数据传输，特别是芯片内或者芯片间的数据传输会迅速成为训练大规模 AI 模型的瓶颈。所以我们需要重新思考 AI 模型的训练，部署以及模型本身，还要思考，如何在这个越来越有挑战性的内存墙下去设计人工智能硬件。 SSD Prices Continue to Fall, Now Upgrade Your Hard Drive!". MiniTool. 2018-09-03 . Retrieved 2019-03-28.According to Moore’s Law, which states that the number of transistors in a circuit doubles every two years, CPUs will eventually become too fast to yield any noticeable difference in computing speed. Once we reach this so-called memory wall, program/app execution time will depend almost entirely on the speed at which RAM can send data to the CPU. So even if you have an incredibly fast processor in your computer, it’s function may be limited to the speed of your RAM. Cai F, Correll J M, Lee S H, et al. A fully integrated reprogrammable memristor-CMOS system for efficient multiply-accumulate operations. Nat Electron, 2019, 2: 290–299